1. Field of the Invention
The present invention relates to a semiconductor device and a method of manufacturing the semiconductor device. More particularly, the present invention relates to a semiconductor device including a resistance reducing layer to reduce a resistance thereof, and a method of manufacturing the semiconductor device.
2. Description of the Related Art
Integrated semiconductor devices continue to have increased packing density, higher operating frequencies, and lower operating voltages. As these trends continue, the feature size of patterns formed on a chip and the space between the formed patterns becomes smaller. Polysilicon has been a very useful material for forming and interconnecting individual components, such as for forming gate electrodes. However, as the pattern size decreases, resistances of interconnections become increasingly important. Because polysilicon has a relatively high resistivity, and pattern sizes continue to decrease, polysilicon interconnections have a relatively higher RC (resistive-capacitive) time delay and IR (current-resistance) voltage drop than earlier circuits having larger pattern sizes.
Therefore, polycide structures, which have similar characteristics to those of polysilicon, while having a lower resistivity than that of polysilicon, have become increasingly popular. One method of using a polycide structure is to have a multilayer structure consisting of a refractory metal silicide, such as titanium silicide or tungsten silicide on a doped polysilicon layer. Such a structure has been used to interconnect and form components, such as gate electrodes of very large scale integrated (VLSI) circuits. However, the resistivity of the tungsten silicide is approximately 100μΩ-cm, which is still relatively high, and further reduction in the resistivity of the gate electrode is required to form acceptable sub-quarter-micron ultra-large scale integrated (ULSI) circuits.
Thus, the industry has recently turned to tungsten-polysilicon (hereinafter, referred to as “W-poly”) gate structures, because a W-poly gate structure has a resistivity of approximately 10 μΩ-cm, which is lower than that of the conventional polysilicon or polycide gate electrodes.
FIG. 1 is a cross sectional view of a conventional MOS transistor having a W-poly gate structure.
Referring to FIG. 1, a gate dielectric layer 15 is formed on a silicon substrate 10. A gate stack 35, which includes a doped polysilicon layer 20, a barrier layer 25 and a tungsten (W) layer 30, is formed on the gate dielectric layer 15. A gate capping layer 40 of silicon nitride (SiN) is formed on the gate stack 35. Because tungsten reacts with silicon (Si) at a temperature as low as 600° C. in a process known as silicidation, it is necessary to form a high quality diffusion barrier layer 25 between the W layer 18 and the polysilicon layer 20 to prevent such silicidation. Titanium nitride (TiN) and tungsten nitride (WN) and are both candidates for the barrier 25 to avoid silicidation of the W layer 30.
In a conventional post-gate etching process, dry or wet oxidation (i.e., selective oxidation) is used to cure the etch damage and to improve the gate dielectric strength. Thus, all gate materials, including the metal materials (W and the barrier material) are subjected to this oxidation. Under selective oxidation conditions, the W-based materials will not be oxidized. However, if the barrier layer 25 includes TiN, the TiN layer can oxidize, thereby resulting in lift-off of the W layer 30. Accordingly, the W-poly gate electrode without TiN is preferred, from a point of a low resistivity and process integration.
There are also problems with using WN as the barrier layer 25. When the barrier layer 25 is formed of WN, nitrogen (N2) flows into the polysilicon layer 20 during the deposition of the WN barrier layer 25. This causes nitrogen to react with the polysilicon layer 20 to form a high resistance SiN-based insulation layer between the WN barrier layer 25 and the polysilicon layer 20. Further, during the selective oxidation process, oxidants diffuse into the interface between the WN barrier layer 25 and the polysilicon layer 20 to thereby form an insulating layer, such as a silicon oxynitride layer. This causes even more resistance, which in turn increases the contact resistance (Rc) between the W layer 30 and the polysilicon layer 20.
As mentioned above, increased resistance is to be avoided, because increased resistance causes a higher RC delay, which in turn causes a time delay tRCD (Ras to CAS time delay) failure in memory devices, thereby deteriorating the yield and the operating speed of the end component.
A tungsten silicide layer is formed on a polysilicon layer by a chemical vapor deposition (CVD) process or a physical vapor deposition (PVD) process to reduce an interface resistance between the polysilicon layer and a metal layer formed on the polysilicon layer.
When the tungsten silicide layer is interposed between the polysilicon layer and the metal layer using the CVD process, the uniformity of the tungsten silicide layer is poor causing the interface resistance between the polysilicon layer and the metal layer to be irregular. In addition, since the tungsten silicide layer is mainly formed using a dichlorosilane (SiH2Cl2) gas or a tungsten hexafluoride (WF6) gas as a source gas, halogen elements contained in the source gas serve as impurities so that the interface resistance between the polysilicon layer and the metal layer increases.
When the tungsten silicide layer is formed between the polysilicon layer and the metal layer using the PVD process, ingredients in the tungsten silicide layer agglomerate in a successive high temperature process because the tungsten silicide layer having an amorphous phase is formed on the polysilicon layer. Thus, the distribution of the interface resistance between the polysilicon layer and the metal layer becomes irregular and a conductive structure including the agglomerated tungsten silicide layer has an increased sheet resistance.